%%%%%%%% ASPLOS 2027 PAPER TEMPLATE %%%%%%%%%%%%%%%%%
%
% ACM International Conference on Architectural Support for
% Programming Languages and Operating Systems
%
% Format: ACM SIGPLAN, <= 12 pages (excluding references), 10pt, two-column
% Uses acmart.cls with sigplan option
%
% Official CFP: https://www.asplos-conference.org/asplos2026/call-for-papers-asplos27/
% ACM Template: https://www.acm.org/publications/proceedings-template
%
% IMPORTANT NOTES:
% - RAPID REVIEW ROUND: Reviewers read ONLY the first 2 pages!
%   --> First 2 pages MUST be self-contained
%   --> Clearly state problem, approach, contribution in first 2 pages
%   --> Do NOT rely on content after page 2 for rapid review
% - Must advance Architecture, PL, and/or OS research
%   --> NOT just using arch/PL/OS to advance another domain
% - Two cycles: April 2026 and September 2026
% - Max 4 submissions per author per cycle
% - Major Revision decision available
% - Double-blind review
%
% RAPID REVIEW TIPS (critical for acceptance):
%   Page 1: Problem motivation + why it matters to arch/PL/OS
%   Page 2: Approach overview + key results preview + contribution list
%   If reviewers cannot determine your contribution to arch/PL/OS
%   from the first 2 pages, your paper WILL be rejected in rapid review.

\documentclass[sigplan,10pt]{acmart}

% Remove copyright/permission footer for submission
\renewcommand\footnotetextcopyrightpermission[1]{}
\settopmatter{printfolios=true}

% Remove ACM reference format for submission
\setcopyright{none}
\renewcommand\acmConference[4]{}
\acmDOI{}
\acmISBN{}

% Recommended packages for architecture/systems papers
\usepackage{booktabs}       % Professional tables
\usepackage{xspace}
\usepackage{subcaption}     % Side-by-side figures
\usepackage{algorithm}      % Algorithm environment
\usepackage{algorithmic}    % Pseudocode formatting
\usepackage{listings}       % Code listings (useful for ISA/compiler examples)
\usepackage[capitalize,noabbrev]{cleveref}  % Smart cross-references

% Code listing style for architecture/compiler papers
\lstset{
  basicstyle=\footnotesize\ttfamily,
  numbers=left,
  numberstyle=\tiny,
  xleftmargin=2em,
  breaklines=true,
  tabsize=2,
  showstringspaces=false,
  frame=single,
  captionpos=b,
  morekeywords={load, store, fence, atomic, sync}  % Add ISA keywords
}

% Custom commands -- replace \system with your anonymized name
\newcommand{\system}{SystemName\xspace}
\newcommand{\eg}{e.g.,\xspace}
\newcommand{\ie}{i.e.,\xspace}
\newcommand{\etal}{\textit{et al.}\xspace}
\newcommand{\para}[1]{\smallskip\noindent\textbf{#1.}}
\newcommand{\parait}[1]{\smallskip\noindent\textit{#1.}}

% Architecture-specific macros
\newcommand{\us}{\,$\mu$s\xspace}
\newcommand{\ns}{\,ns\xspace}
\newcommand{\GHz}{\,GHz\xspace}
\newcommand{\GB}{\,GB\xspace}
\newcommand{\MB}{\,MB\xspace}
\newcommand{\KB}{\,KB\xspace}

\begin{document}

\title{Your Paper Title Here}

% Anonymized for submission
\author{Paper \#XXX}
\affiliation{%
  \institution{Anonymous}
  \country{}}

% Camera-ready (uncomment and fill in):
% \author{Author One}
% \affiliation{%
%   \institution{University/Company}
%   \city{City}
%   \country{Country}}
% \email{email@example.com}
%
% \author{Author Two}
% \affiliation{%
%   \institution{University/Company}
%   \city{City}
%   \country{Country}}
% \email{email@example.com}

\begin{abstract}
% Guidelines for a strong ASPLOS abstract:
% - State what you built/discovered (the contribution)
% - Identify the arch/PL/OS challenge addressed
% - Describe your approach and key insight
% - Quantify improvement with concrete numbers
%
% Keep to 150--200 words. Remember: this is part of the first 2 pages!

We present \system, a [hardware/software/compiler technique] that [capability].
[Problem: why existing arch/PL/OS approaches fall short.]
Our key insight is that [observation about hardware-software interaction].
\system exploits this through [technique], achieving [X]$\times$ speedup
and [Y]\% energy reduction compared to [baseline] on [benchmarks].
\end{abstract}

\maketitle
\pagestyle{plain}

%----------------------------------------------------------------------
% ╔══════════════════════════════════════════════════════════════════════╗
% ║  PAGES 1--2 ARE CRITICAL FOR RAPID REVIEW!                        ║
% ║  Reviewers read ONLY the first 2 pages in the rapid review round. ║
% ║  These must:                                                       ║
% ║  1. Clearly state the problem and why it matters                   ║
% ║  2. Explain how this advances Architecture, PL, or OS              ║
% ║     (NOT just using arch/PL/OS to advance another domain)          ║
% ║  3. Outline your approach and key contributions                    ║
% ║  4. Preview your main results with numbers                         ║
% ╚══════════════════════════════════════════════════════════════════════╝

\section{Introduction}
\label{sec:intro}

% Page 1 should cover: problem motivation + why it matters to arch/PL/OS.
% Page 2 should cover: approach overview + contributions + results preview.

Modern [hardware/software] systems face [challenge] due to
[trend]~\cite{hennessy2019new}. While prior work has addressed
[related problem]~\cite{jouppi2017tpu}, [gap remains].
This paper addresses the [arch/PL/OS] challenge of [specific problem].

\para{Key Insight}
We observe that [insight about hardware-software interaction]. This
observation is supported by our analysis of [N] benchmarks on
[hardware platform] (\cref{sec:background}).

\para{Approach Overview}
\system addresses this through [technique]. Unlike [prior approach],
\system [key distinction], enabling [benefit].

We make the following contributions:
\begin{itemize}
  \item We identify and characterize [problem] through analysis of
        [benchmarks/hardware] (\cref{sec:background}).
  \item We propose \system, a [technique] that [capability]
        (\cref{sec:design}).
  \item We implement \system in [context: compiler/hardware/OS] and
        evaluate on [benchmarks] (\cref{sec:evaluation}).
  \item We demonstrate [X]$\times$ [speedup/efficiency] improvement
        over [state-of-the-art], with only [Y]\% area/power overhead.
\end{itemize}

% End of critical first 2 pages. Content below supports the claims above.
%----------------------------------------------------------------------

\section{Background and Motivation}
\label{sec:background}

\subsection{Hardware/Software Context}

Describe relevant architecture, PL, or OS
background~\cite{lattner2004llvm}.

\subsection{Characterization Study}

% Concrete measurements on real hardware strengthen motivation.
\Cref{fig:motivation} shows [measurement] across [benchmarks] on
[hardware platform].

\begin{figure}[t]
  \centering
  \fbox{\parbox{0.9\columnwidth}{\centering\vspace{3em}
    \textit{Performance characterization: breakdown of execution time, \\
    cache miss rates, or energy consumption across benchmarks}
  \vspace{3em}}}
  \caption{Characterization of [metric] across [N] benchmarks on
    [hardware]. On average, [X]\% of [time/energy] is spent on
    [bottleneck], motivating [your approach].}
  \label{fig:motivation}
\end{figure}

\subsection{Opportunity Analysis}

Based on this characterization, we identify [N] key opportunities:

\para{Opportunity 1} [Description with concrete numbers.]

\para{Opportunity 2} [Description.] These opportunities motivate
the design of \system.

%----------------------------------------------------------------------
\section{Design}
\label{sec:design}

\Cref{fig:architecture} shows the overall architecture of \system.

\begin{figure*}[t]
  \centering
  \fbox{\parbox{0.9\textwidth}{\centering\vspace{4em}
    \textit{System architecture: hardware blocks, compiler passes, \\
    or OS mechanisms and their interactions}
  \vspace{4em}}}
  \caption{Architecture of \system. [Describe the key components:
    hardware units, compiler passes, or OS mechanisms.]}
  \label{fig:architecture}
\end{figure*}

\subsection{[Hardware/Compiler/OS Component A]}

Describe the first key component. The core scheduling algorithm is
shown in \cref{alg:scheduling}.

\begin{algorithm}[t]
  \caption{[Algorithm name] in \system}
  \label{alg:scheduling}
  \begin{algorithmic}[1]
    \STATE \textbf{Input:} computation graph $G(V, E)$, resource constraints $R$
    \STATE \textbf{Output:} mapping $M: V \rightarrow R$
    \FOR{each node $v \in \text{TopologicalSort}(V)$}
      \STATE $t_v \leftarrow \max_{(u,v) \in E} (t_u + \text{latency}(u))$
      \STATE $r^* \leftarrow \arg\min_{r \in R} \text{Cost}(v, r, t_v)$
      \STATE $M[v] \leftarrow r^*$
    \ENDFOR
    \STATE \textbf{return} $M$
  \end{algorithmic}
\end{algorithm}

\subsection{[Hardware/Compiler/OS Component B]}

Describe the second component. The performance improvement
from this component can be modeled as:
\begin{equation}
  \label{eq:speedup}
  S = \frac{1}{(1-f) + \frac{f}{p} + \frac{\alpha \cdot f}{B}}
\end{equation}
where $f$ is the parallelizable fraction, $p$ is the number of
processing elements, $B$ is the memory bandwidth, and $\alpha$
is the arithmetic intensity (ops/byte).

% Example: Code transformation (common in ASPLOS PL papers)
\subsection{Example: Code Transformation}

\Cref{fig:transform} shows how \system transforms [code pattern]
to exploit [hardware feature].

\begin{figure}[t]
  \centering
  \begin{minipage}[t]{0.48\columnwidth}
    \centering
    \begin{lstlisting}[title=\textbf{Before},language=C]
for (i = 0; i < N; i++)
  for (j = 0; j < M; j++)
    C[i][j] += A[i][k]
               * B[k][j];
    \end{lstlisting}
  \end{minipage}
  \hfill
  \begin{minipage}[t]{0.48\columnwidth}
    \centering
    \begin{lstlisting}[title=\textbf{After (\system)},language=C]
for (ii = 0; ii < N;
     ii += TILE)
  for (jj = 0; jj < M;
       jj += TILE)
    kernel(A, B, C,
           ii, jj);
    \end{lstlisting}
  \end{minipage}
  \caption{Code transformation example. \system converts [pattern]
    (left) into [optimized pattern] (right), improving [metric]
    by [X]$\times$.}
  \label{fig:transform}
\end{figure}

%----------------------------------------------------------------------
\section{Implementation}
\label{sec:implementation}

We implement \system as follows:
\begin{itemize}
  \item \textbf{[Hardware component]:} [X]K gates in [HDL], synthesized
        at [Y]\GHz using [process node].
  \item \textbf{[Compiler component]:} [X]K lines of [language], integrated
        with [LLVM/GCC/custom compiler].
  \item \textbf{[OS component]:} [X] lines of kernel module in [language].
\end{itemize}

%----------------------------------------------------------------------
\section{Evaluation}
\label{sec:evaluation}

We evaluate \system to answer:
\begin{enumerate}
  \item How does \system compare to state-of-the-art on standard benchmarks?
  \item What is the hardware/software overhead?
  \item How does each component contribute to the improvement?
  \item How sensitive is \system to [key parameters]?
\end{enumerate}

\subsection{Methodology}
\label{sec:eval:method}

\para{Simulation/Hardware}
We evaluate using [simulator/FPGA/real hardware]: [details].

\para{Benchmarks}
We use [SPEC CPU/PARSEC/SPLASH/MLPerf/custom] benchmarks.
\Cref{tab:benchmarks} summarizes the evaluation suite.

\para{Baselines}
We compare against:
(1)~[Baseline A]~\cite{jouppi2017tpu},
(2)~[Baseline B]~\cite{kwon2018maeri}, and
(3)~[Baseline C].

\begin{table}[t]
  \caption{Benchmark suite characteristics.}
  \label{tab:benchmarks}
  \centering
  \begin{small}
  \begin{tabular}{@{}llrr@{}}
    \toprule
    \textbf{Benchmark} & \textbf{Domain} & \textbf{Instructions} &
    \textbf{Working Set} \\
    \midrule
    BenchA  & Image    & 2.1B  & 64\,MB  \\
    BenchB  & NLP      & 4.8B  & 128\,MB \\
    BenchC  & Graph    & 1.3B  & 256\,MB \\
    BenchD  & HPC      & 8.2B  & 512\,MB \\
    BenchE  & Serving  & 0.6B  & 32\,MB  \\
    \bottomrule
  \end{tabular}
  \end{small}
\end{table}

\subsection{Performance Results}
\label{sec:eval:perf}

\Cref{tab:performance} shows the main performance comparison.
\system achieves [X]$\times$ geometric mean speedup over [baseline].

\begin{table}[t]
  \caption{Performance comparison (speedup over baseline).
    Higher is better. Bold indicates best result.}
  \label{tab:performance}
  \centering
  \begin{small}
  \begin{tabular}{@{}lcccc@{}}
    \toprule
    \textbf{Benchmark} & \textbf{Base} & \textbf{Prior A} &
    \textbf{Prior B} & \textbf{\system} \\
    \midrule
    BenchA  & 1.00$\times$ & 1.42$\times$ & 1.55$\times$ & \textbf{2.13}$\times$ \\
    BenchB  & 1.00$\times$ & 1.28$\times$ & 1.39$\times$ & \textbf{1.87}$\times$ \\
    BenchC  & 1.00$\times$ & 1.15$\times$ & 1.22$\times$ & \textbf{1.64}$\times$ \\
    BenchD  & 1.00$\times$ & 1.51$\times$ & 1.68$\times$ & \textbf{2.35}$\times$ \\
    BenchE  & 1.00$\times$ & 1.33$\times$ & 1.41$\times$ & \textbf{1.92}$\times$ \\
    \midrule
    \textit{Geomean} & 1.00$\times$ & 1.33$\times$ & 1.44$\times$ &
    \textbf{1.96}$\times$ \\
    \bottomrule
  \end{tabular}
  \end{small}
\end{table}

\subsection{Area and Power Overhead}
\label{sec:eval:overhead}

\begin{figure}[t]
  \centering
  \fbox{\parbox{0.9\columnwidth}{\centering\vspace{3em}
    \textit{Stacked bar chart: area/power breakdown by component}
  \vspace{3em}}}
  \caption{Area and power overhead of \system. The total overhead
    is [X]\% area and [Y]\% power, dominated by [component].}
  \label{fig:overhead}
\end{figure}

\subsection{Ablation Study}
\label{sec:eval:ablation}

\begin{figure}[t]
  \centering
  \fbox{\parbox{0.9\columnwidth}{\centering\vspace{3em}
    \textit{Grouped bar chart: performance with components disabled}
  \vspace{3em}}}
  \caption{Ablation study. Removing [Component A] reduces speedup
    from [X]$\times$ to [Y]$\times$, confirming its importance.}
  \label{fig:ablation}
\end{figure}

\subsection{Sensitivity Analysis}
\label{sec:eval:sensitivity}

We vary [key parameter] from [min] to [max] to understand its
impact on performance.

%----------------------------------------------------------------------
\section{Discussion}
\label{sec:discussion}

\para{Generalizability}
[Discuss applicability to other architectures/workloads.]

\para{Limitations}
[Honest discussion of limitations and assumptions.]

%----------------------------------------------------------------------
\section{Related Work}
\label{sec:related}

\para{[Hardware Approaches]}
Prior architecture work~\cite{jouppi2017tpu, kwon2018maeri} addresses
[problem]. \system differs by [distinction].

\para{[Compiler/PL Approaches]}
Compiler techniques~\cite{lattner2004llvm} have targeted [problem].
\system complements these by [distinction].

\para{[OS/Runtime Approaches]}
OS-level approaches~\cite{hennessy2019new} provide [capability].
\system extends this with [technique].

%----------------------------------------------------------------------
\section{Conclusion}
\label{sec:conclusion}

We presented \system, a [technique] that advances [arch/PL/OS area]
by [capability]. \system achieves [X]$\times$ speedup over
state-of-the-art with only [Y]\% overhead, demonstrating the
effectiveness of [key insight].

%----------------------------------------------------------------------
% Acknowledgments (only in camera-ready, remove for submission)
% \begin{acks}
% We thank the anonymous reviewers for their feedback. This work was
% supported by [funding sources].
% \end{acks}

\bibliographystyle{ACM-Reference-Format}
\bibliography{references}

\end{document}
